Syonyk
January 21, 2021, 7:41pm
5
Here’s the uC datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040_datasheet.pdf
2.6.2 has the details, but in summary:
There is a total of 264kB of on-chip SRAM. Physically this is partitioned into six banks, as this vastly improves memory bandwidth for multiple masters, but software may treat it as a single 264kB memory region. There are no restrictions on what is stored in each bank: processor code, data buffers, or a mixture. There are four 16k x 32-bit banks (64kB each) and two 1k x 32-bit banks (4kB each).
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SRAM is mapped to system addresses starting at 0x20000000. The first 256kB address region is word-striped across the four larger banks, which provides a significant memory parallelism benefits for most use cases.
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The next two 4kB regions (starting at 0x20040000 and 0x20041000) are mapped directly to the smaller, 4kB memory banks. Software may choose to use these for per-core purposes, e.g. stack and frequently-executed code, guaranteeing that the processors never stall on these accesses. However, like all SRAM on RP2040, these banks have single-cycle access from all masters providing no other masters are accessing the bank in the same cycle, so it is reasonable to treat memory as a single 264kB device.
The four 64kB banks are also available at a non-striped mirror. The four 64kB regions starting at 0x21000000, 0x21010000, 0x21020000, 0x21030000 are each mapped directly to one of the four 64kB SRAM banks. Software can explicitly allocate data and code across the physical memory banks, for improved memory performance in exceptionally demanding cases. This is often unnecessary, as memory striping usually provides sufficient parallelism with less software complexity.
As @Vertiginous mentions, microcontrollers are often very weird looking memory systems. GPUs are similarly bizarre at times. But this sort of “Well, you can use it all as one block, but if you need something special, here’s how it’s physically laid out…” thing is quite common to find.